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all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 1/60 doc. version: 0.0 total pages: 60 date: 2008/5/2 note: the content of this specification is subject to change without prior notice. ? 2008 au optronics all rights reserved, do not copy. model name: a 0 30 d w 01 v0 product specification 3.0 color tft-lcd module < > preliminary specification < > final specification www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 2/60 record of revision version revise date page content 0.0 2008/5/2 first draft www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 3/60 contents a. physical specifications ......................... ................................................... ......................... 5 b. electrical specifications ....................... ................................................... .......................... 6 1. pin assignment .................................. ................................................... ................................................... ......6 2. absolute maximum ratings ........................ ................................................... .................................................9 3. electrical characteristics ...................... ................................................... ................................................... ..10 3.1 recommended operating conditions (gnd=agnd=0v) . ................................................... ..............10 3.3 recommended capacitance values of external capa citor .............................................. .................11 3.4 backlight driving conditions................... ................................................... ..........................................11 4. input timing ac characteristic.................. ................................................... .................................................12 5. input timing format............................. ................................................... ................................................... ....13 5.1 ups051 timing conditions (refer to fig.1 fig.2 fig.3)............................................. ..........................13 5.2 ups052 timing .................................. ................................................... ..............................................16 5.2.1 ups052 (320 mode/ntsc/24.535mhz) timing speci fications. (refer to fig.4 fig.5) ........16 5.2.2 ups052 (320 mode/pal/24.375mhz) timing specif ications (refer to fig.4 fig.5) ............16 5.2.3 ups052 (360 mode/ntsc/27mhz) timing specifica tions (refer to fig.4 fig.5) ................17 5.2.4 ups052 (360 mode/pal/27mhz) timing specificat ions (refer to fig.4 fig.5) ...................17 5.3 ccir656 timing ................................. ................................................... .............................................20 5.3.1 ccir656 decoding ................................................... ................................................... ...........20 5.3.2 ccir656 ntsc ................................................... ................................................... .................21 5.3.3 ccir656 pal ................................................... ................................................... ....................22 5.4 yuv 720 and yuv 640 timing ..................... ................................................... ....................................23 5.4.1 yuv 720 mode/ntsc timing specifications (refe r to fig.9 fig.11) ....................................23 5.4.2 yuv 720 mode/pal timing specifications (refer to fig.9 fig.11) .......................................23 5.4.3 yuv 640 mode/ntsc timing specifications (refe r to fig.10 fig.11) ..................................24 5.4.4 yuv 640 mode/pal timing specifications (refer to fig.10 fig.11) .....................................24 5.5 ccir656/yuv 720/yuv 640 to rgb conversion ...... ................................................... .....................27 6. serial control interface ac characteristic...... ................................................... ............................................28 6.1 timing chart................................... ................................................... ..................................................2 8 6.2 the configuration of serial data at sda termina l is at below...................................... ........................29 6.3 register table ................................. ................................................... .................................................30 6.4 register description ........................... ................................................... .............................................31 c. optical specification (note 1,note 2, note 3 ).. ................................................... ........... 45 d. reliability test items .......................... ................................................... ........................... 47 e. packing form .................................... ................................................... ............................. 48 f. outline dimension ............................... ................................................... .......................... 49 g. application note ................................ ................................................... ............................ 50 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 4/60 1. application circuit............................. ................................................... ................................................... ......50 1.1 with internal led driver circuit............... ................................................... .........................................50 1.2 with external led driver circuit............... ................................................... ........................................51 2. power on/off sequence........................... ................................................... ..................................................5 2 2.1 power on (standby disabling) ................... ................................................... ......................................52 3.2 power off (standby enabling)................... ................................................... .......................................53 3. recommended power on/off serial command settings ................................................... ............................54 3.1 ups051 ......................................... ................................................... ..................................................5 4 3.2 ups052 320 mode ................................ ................................................... ..........................................55 3.3 ups052 360 mode ................................ ................................................... ..........................................56 3.4 ccir656........................................ ................................................... ..................................................5 7 3.5 yuv 720 ........................................ ................................................... ..................................................5 8 3.6 yuv 640 ........................................ ................................................... ..................................................5 9 4. power generation circuit ........................ ................................................... ................................................... 60 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 5/60 a. physical specifications no. item specification remark 1 display resolution dot 960(w) x 240(h) 2 active area mm 65.52(w) x 36.84(h) 3 screen size inch 2.96 (diagonal) 4 dot pitch um 68.25 x 153.5 5 color configuration r, g, b delta 6 overall dimension mm 74.92(w) x 42.74(h) x 2.65 (d) note 1 7 weight g t.b.d 8 panel surface treatment hard coating note 1: refer to f. outline dimension www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 6/60 b. electrical specifications 1. pin assignment pin no symbol i/o i/o structure description remark 1 vcom i - panel common voltage 2 cs i type 3 serial command enable 3 sda i type 2 serial command data input 4 scl i type 1 serial command clock input 5 hsync i type 1 horizontal sync input 6 vsync i type 1 vertical sync input 7 dclk i type 1 data clock input 8 d7 i type 1 data input; msb 9 d6 i type 1 data input 10 d5 i type 1 data input 11 d4 i type 1 data input 12 d3 i type 1 data input 13 d2 i type 1 data input 14 d1 i type 1 data input 15 d0 i type 1 data input; lsb 16 gnd p - ground for digital circuit 17 vdd p - system power 3.0v~3.6v 18 dvdd c - power setting capacitor connect pin 19 v1 c - power setting capacitor connect pin 20 v2 c - power setting capacitor connect pin 21 v3 c - power setting capacitor connect pin 22 v4 c - power setting capacitor connect pin 23 vdd2 c - power setting capacitor connect pin 24 v5 c - power setting capacitor connect pin 25 v6 c - power setting capacitor connect pin 26 vdd3 c - power setting capacitor connect pin 27 vdd5 c - power setting capacitor connect pin 28 v7 c - power setting capacitor connect pin 29 v8 c - power setting capacitor connect pin 30 vgh c - power setting capacitor connect pin 31 vgl c - power setting capacitor connect pin 32 agnd p - ground for analog circuit www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 7/60 33 frp o type 4 frame polarity output for vcom 34 comdc o type 5 vcom dc voltage output pin 35 vcac c - power setting capacitor for vcom ac 36 drv p - vled boost transistor driving signal 37 vled p type 6 led power anode 38 fb p type 7 led power cathode 39 vcom i - panel common voltage i input, o output, c capacitor, p power, d dummy note: definition of scanning direction, refer to fi gure as below pin 1 pin 39 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 8/60 i/o pin structure: pull high/low resistor is 700k ? www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 9/60 2. absolute maximum ratings item symbol condition min. max. unit remark supply voltage vdd agnd=gnd=0v -0.3 4.5 v vgh agnd=gnd=0v -0.3 16 v tft-lcd power voltage vgl agnd=gnd=0v -16 0.3 v input signal voltage cs,sda,scl,vsync, hsync,dclk,d0~d7 agnd=gnd=0v -0.3 4.5 v vcom ac output voltage frp agnd=gnd=0v -0.3 8 v vcom ac power voltage vcac agnd=gnd=0v -0.3 8 v vcom dc output voltage comdc agnd=gnd=0v -0.3 8 v vcom input voltage vcom agnd=gnd=0v -0.3 8 v vdd2 agnd=gnd=0v -0.3 8 v vdd3 agnd=gnd=0v -0.3 16 v vdd5 agnd=gnd=0v -0.3 20 v v1 agnd=gnd=0v -0.3 8 v v2 agnd=gnd=0v -0.3 8 v v3 agnd=gnd=0v -0.3 8 v v4 agnd=gnd=0v -0.3 8 v v5 agnd=gnd=0v -0.3 16 v v6 agnd=gnd=0v -0.3 16 v v7 agnd=gnd=0v -0.3 16 v charge pump voltage v8 agnd=gnd=0v -16 8 v storage temperature tstg - 0 70 ambient temperature operating temperature topa - 0 60 ambient temperature www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 10/60 3. electrical characteristics 3.1 recommended operating conditions (gnd=agnd=0v) item symbol min. typ. max. unit remark power supply vdd 3.0 3.3 3.6 v note 1 h level v ih 0.7* vdd - vdd v input signal l level v il gnd - 0.3* vdd v note 1: a build-in power on reset circuit for vdd is provided within the integrated lcd driver ic. th e lcd module is in power save mode in default, and a standby releasing is required after vdd power on through serial control. please refer to th e register stb setting for detail. parameter symbol condition min. typ. max. unit remark i dd tbd note 1 input current for v dd i dd(standby) v dd =3.3v tbd ma note 1 v gh v dd =3.3v 14.5 15 15.5 v note 2 dc-dc voltage v gl v dd =3.3v -10.5 -10 -9.5 v note 2 v cac - 3.6 4.2 4.8 vp-p ac component, note 3 vcom voltage v cdc - tbd v dc component, note 4 note 1: test condition: 8colorbar+grayscale pattern , ups051 mode, dclk=27mhz, frame rate: 60hz, other registers are default setting. note 2: v gh and v gl are output voltages of integrated lcd driver ic. note 3: the brightness of lcd panel could be adjust ed by the adjustment of the ac component of vcom. note 4: v cdc could be adjusted, so as to minimize flicker and m aximum contrast on each module. www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 11/60 3.3 recommended capacitance values of external capa citor the recommended capacitance values of the external capacitor are shown below. these values should be finally determined only after performing sufficient evaluation on the module. pin name recommended value of capacitors ( ? f) withstanding voltage (v) vgh 4.7 to 10 25 vgl 4.7 to 10 16 vdd5 4.7 to 10 25 vdd3 4.7 to 10 16 vdd2 4.7 to 10 10 dvdd 4.7 to 10 6.3 vcac 4.7 to 10 10 v1, v2 2.2 to 10 10 v3, v4 2.2 to 10 10 v5, v6 2.2 to 10 16 v7, v8 2.2 to 10 16 3.4 backlight driving conditions parameter symbol min. typ. max. unit remark led current 20 ma led voltage v l 6.4 7.2 v 2 led?s feedback voltage v fb - 0.6 - v led life time l l tbd --- --- hr note 1,2,3 note 1: led backlight is two leds serial type. note 2: the ?led supply voltage? is defined by the number of led at ta=25 ? c, i l =20ma. in the case of 2 pcs led, v l =3.2*2=6.4v note 3: the ?led life time? is defined as the time for the module brightness to decrease to 50% of the initial value at ta=25 ? c, i l =20ma note 4: the led lifetime could be decreased if oper ating i l is larger than 20ma www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 12/60 4. input timing ac characteristic (vdd=3.0 ~3.6v, agnd=gnd=0v, ta=25 ) parameter symbol min. typ. max. unit remark clk time t dclk 33 - 188 ns dclk width t cw 16.5 - 94 ns d cw =50% dclk duty cycle tcw 40 50 60 % vsync setup time tvst 6 - - ns vsync hold time tvhd 6 - - ns hsync setup time thst 6 - - ns hsync hold time thhd 6 - - ns data setup time tdst 6 - - ns data hold time tdhd 6 - - ns hsync width thsw 1 1 254 t dclk vsync width tvsw 1 t dclk 1 t dclk 6h t h means: hsync period www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 13/60 5. input timing format 5.1 ups051 timing conditions (refer to fig.1 fig.2 fig.3) note 1: the t hbp time is adjustable by setting register hblk; requi rement of minimum blanking time and minimum front porch time must be satisfied. note 2: the t vbp time is adjustable by setting register vblk. ups05 1 accepts both interlace and non-interlace vertical input timing. parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 13.5 27 27.19 mhz period t h 1024 1716 1728 t dclk display period t hd 960 t dclk back porch t hbp 50 70 255 t dclk note 1 front porch t hfp 14 686 513 t dclk hsync pulse width t hsw 1 1 t hbp - 1 t dclk odd period even t v 242.5 262.5 450.5 t h odd display period even t vd 240 t h odd 1 21 31 back porch even t vbp 1.5 21.5 31.5 t h note 2 odd 1.5 1.5 179.5 front porch even t vfp 1 1 179 t h odd pulse width even t vsw 1 t dclk 1 t dclk 6 t h vsync 1 frame 485 525 901 t h www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 14/60 fig.1 ups051 input horizontal timing chart fig.2 ups051 input horizontal data sequence 1 invalid data invalid data t hbp t hd 2 3 960 data t hfp t h = t hbp + t hd + t hfp hsync dclk t hsw hsync r g b r g b r g b r g g b r g b r g b r g b r b line 2,4,6 240 line 1,3,5 239 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 15/60 fig.3 ups051 input vertical timing chart www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 16/60 5.2 ups052 timing 5.2.1 ups052 (320 mode/ntsc/24.535mhz) timing speci fications. (refer to fig.4 fig.5) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 20.54 24.535 30 mhz period t h 1306 1560 1907 t dclk display period t hdisp - 1280 - t dclk back porch t hbp 2 241 255 t dclk front porch t hfp 24 39 372 t dclk hsync pulse width t hsw 1 1 200 t dclk odd period even t v 242.5 262.5 450.5 t h odd display period even t vdisp - 240 - t h odd 1 21 31 back porch even t vbp 1.5 21.5 31.5 t h odd 1.5 1.5 179.5 front porch even t vfp 1 1 179 t h odd pulse width even t vsw 1 t dclk 1 t dclk 6 t h vsync 1 frame 485 525 901 t h 5.2.2 ups052 (320 mode/pal/24.375mhz) timing specif ications (refer to fig.4 fig.5) parameter symb min. typ. max. unit. remark dclk frequency 1/t dclk 20.4 24.375 30 mhz period t h 1306 1560 1920 t dclk display period t hdisp - 1280 - t dclk back porch t hbp 3 241 255 t dclk front porch t hfp 23 39 385 t dclk hsync pulse width t hsw 1 1 200 t dclk odd period even t v 292.5 312.5 450.5 t h odd display period even t vdisp - 288 - t h odd 3 24 34 back porch even t vbp 3.5 24.5 34.5 t h odd 1.5 0.5 128.5 front porch even t vfp 1 0 128 t h odd pulse width even t vsw 1 t dclk 1 t dclk 6 t h vsync 1 frame 585 625 901 t h www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 17/60 5.2.3 ups052 (360 mode/ntsc/27mhz) timing specifica tions (refer to fig.4 fig.5) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 23 27 30 mhz period t h 1466 1716 1907 t dclk display period t hdisp - 1440 - t dclk back porch t hbp 2 241 255 t dclk front porch t hfp 24 35 212 t dclk hsync pulse width t hsw 1 1 200 t dclk odd period even t v 242.5 262.5 450.5 t h odd display period even t vdisp - 240 - t h odd 1 21 31 back porch even t vbp 1.5 21.5 31.5 t h odd 1.5 1.5 179.5 front porch even t vfp 1 1 179 t h odd pulse width even t vsw 1 t dclk 1 t dclk 6 t h vsync 1 frame 485 525 901 t h 5.2.4 ups052 (360 mode/pal/27mhz) timing specificat ions (refer to fig.4 fig.5) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 23 27 30 mhz period t h 1466 1728 1920 t dclk display period t hdisp - 1440 - t dclk back porch t hbp 3 241 255 t dclk front porch t hfp 23 47 225 t dclk hsync pulse width t hsw 1 1 200 t dclk odd period even t v 292.5 312.5 450.5 t h odd display period even t vdisp - 288 - t h odd 3 24 34 back porch even t vbp 3.5 24.5 34.5 t h odd 1.5 0.5 128.5 front porch even t vfp 1 0 128 t h odd pulse width even t vsw 1 t dclk 1 t dclk 6 t h vsync 1 frame 585 625 901 t h www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 18/60 r0 invalid data invalid data t hbp t hdisp g0 b0 n data t hfp t h = t hbp + t hdisp + t hfp hsync dclk t hsw dm r1 g1 b1 dm fig.4 ups052 input horizontal timing chart www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 19/60 hsync vsync valid data valid data data 1 field ( odd ) 1 field ( even ) v display v display v blanking v blanking 1 frame t tt t v vv v b bb b t tt t v vv v b bb b t tt t v vv v d dd d t tt t v vv v d dd d t tt t v vv v t tt t v vv v t tt t v vv v s ss s w ww w t tt t v vv v f ff f p pp p t tt t v vv v f ff f p pp p fig.5 ups052 input vertical timing chart www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 20/60 5.3 ccir656 timing fig.6 ccir656 data input format 5.3.1 ccir656 decoding ff 00 00 < xy > signals are involved with hsync, v sync and field encode following bits: f=field select : f=0 for field 1, f=1 for field 2; v=1 during vertical blanking h=0 at sav , h=1 at eav , p3-p0=protection bits : p3=v h p2=f h p1=f v p0=f v h : represents the exclusive-or function control is provided through ?end of video? (eav) a nd ?start of video? (sav) timing references. horizontal blanking section consists of repeating pattern 80 10 80 10 xy d7(msb) d6 d5 d4 d3 d2 d1 d0(lsb) 1 f v h p3 p2 p1 p0 ffh invalid data invalid data data dclk (27mhz) 00h 00h xy cb0 y0 cr0 y1 cb 718 y718 cr 718 y719 ffh 00h 00h xy 720 ccir valid data (sav) (eav) note: under the register cbcr=0 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 21/60 5.3.2 ccir656 ntsc fig.7 ccir656 ntsc mode vertical timing format line number f v h (eav) h (sav) 1-3 1 1 1 0 4-22 0 1 1 0 23-262 0 0 1 0 263-265 0 1 1 0 266-285 1 1 1 0 286-525 1 0 1 0 f h v 1 even field eav blanking 0 odd field sav active video www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 22/60 5.3.3 ccir656 pal blanking field 1 active video blanking field 2 active video line 1(v=1) line 23(v=0) line 311(v=1) line 624(v=1) line 625(v=1) line 625 line 313 line 1 filed 1 (f=0) odd filed 2 (f=1) even h = 1 eav h = 0 sav line 336(v=0) blanking fig.8 ccir656 pal mode vertical timing format line number f v h (eav) h (sav) 1-22 0 1 1 0 23-310 0 0 1 0 311-312 0 1 1 0 313-335 1 1 1 0 335-623 1 0 1 0 624-625 1 1 1 0 f h v 1 even field eav blanking 0 odd field sav active video www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 23/60 5.4 yuv 720 and yuv 640 timing 5.4.1 yuv 720 mode/ntsc timing specifications (refe r to fig.9 fig.11) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 23 27 30 mhz period t h 1476 1716 1907 t dclk display period t hdisp - 1440 - t dclk back porch t hbp 2 240 255 t dclk front porch t hfp 34 36 212 t dclk hsync pulse width t hsw - 1 - t dclk odd period even t v 242.5 262.5 450.5 t h odd display period even t vdisp - 240 - t h odd 1 21 31 back porch even t vbp 1.5 21.5 31.5 t h odd 1.5 1.5 179.5 front porch even t vfp 1 1 179 t h odd pulse width even t vsw - 1 - t dclk vsync 1 frame 485 525 901 t h 5.4.2 yuv 720 mode/pal timing specifications (refer to fig.9 fig.11) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 23 27 30 mhz period t h 1476 1728 1920 t dclk display period t hdisp - 1440 - t dclk back porch t hbp 3 240 255 t dclk front porch t hfp 33 48 225 t dclk hsync pulse width t hsw - 1 - t dclk odd period even t v 292.5 312.5 450.5 t h odd display period even t vdisp - 288 - t h odd 3 24 34 back porch even t vbp 3.5 24.5 34.5 t h odd 1.5 0.5 128.5 front porch even t vfp 1 0 128 t h odd pulse width even t vsw - 1 - t dclk vsync 1 frame 585 625 901 t h www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 24/60 5.4.3 yuv 640 mode/ntsc timing specifications (refe r to fig.10 fig.11) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 20.65 24.535 30 mhz period t h 1314 1560 1907 t dclk display period t hdisp - 1280 - t dclk back porch t hbp 2 240 255 t dclk front porch t hfp 32 40 372 t dclk hsync pulse width t hsw - 1 - t dclk odd period even t v 242.5 262.5 450.5 t h odd display period even t vdisp - 240 - t h odd 1 21 31 back porch even t vbp 1.5 21.5 31.5 t h odd 1.5 1.5 179.5 front porch even t vfp 1 1 179 t h odd pulse width even t vsw - 1 - t dclk vsync 1 frame 485 525 901 t h 5.4.4 yuv 640 mode/pal timing specifications (refer to fig.10 fig.11) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 20.5 24.375 30 mhz period t h 1314 1560 1920 t dclk display period t hdisp - 1280 - t dclk back porch t hbp 3 240 255 t dclk front porch t hfp 33 40 385 t dclk hsync pulse width t hsw - 1 - t dclk odd period even t v 292.5 312.5 450.5 t h odd display period even t vdisp - 288 - t h odd 3 24 34 back porch even t vbp 3.5 24.5 34.5 t h odd 1.5 0.5 128.5 front porch even t vfp 1 0 128 t h odd pulse width even t vsw - 1 - t dclk vsync 1 frame 585 625 901 t h www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 25/60 cb0 invalid data invalid data hd data hsync dclk t hsw ntsc:1716 / pal:1728 240 y0 cr0 y1 y2 y3 cb2 cr2 y 719 cr 718 y 718 cb 718 y 717 y 716 cr 716 cb 716 1440 when cbcr=0 and y_cbcr=0 cb0 invalid data invalid data hd data hsync dclk t hsw ntsc:1560 / pal:1560 240 y0 cr0 y1 y2 y3 cb2 cr2 y 639 cr 638 y 638 cb 638 y 637 y 636 cr 636 cb 636 1280 when cbcr=0 and y_cbcr=0 fig.9 yuv720 input horizontal timing chart fig.10 yuv640 input horizontal timing chart www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 26/60 fig.11 yuv input vertical timing chart www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 27/60 5.5 ccir656/yuv 720/yuv 640 to rgb conversion r n =1.164*[(y 2n-1 +y 2n )/2-16] + 1.596*(c rn -128) g n =1.164*[(y 2n-1 +y 2n )/2-16] - 0.813*(c rn -128) - 0.392*(c bn -128) b n =1.164*[(y 2n-1 +y 2n )/2-16] + 2.017*(c bn-128) where y:16~235 c r :16~240 c b :16~240 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 28/60 6. serial control interface ac characteristic item symbol min typical max unit cs input setup time t s0 50 - - ns serial data input setup time t s1 50 - -- ns cs input hold time t h0 50 - - ns serial data input hold time t h1 50 - - ns scl pulse low width t w1l 50 - - ns scl pulse high width t w1h 50 - - ns cs pulse high width t w2 400 - - ns 6.1 timing chart 1. each serial command consists of 16 bits of data which is loaded one bit a time at the rising edge o f serial clock scl. 2. command loading operation starts from the fallin g edge of cs and is completed at the next rising ed ge of cs. 3. the serial control block is operational after po wer on reset, but commands are established by the v sync signal. if command is transferred multiple times fo r the same register, the last command before the vs ync signal is valid. 4. if less than 16 bits of scl are input while cs i s low, the transferred data is ignored. 5. if 16 bits or more of scl are input while cs is low, the previous 16 bits of transferred data after the falling edge of cs pulse are valid data. 6. serial block operates with the scl clock. 7. serial data can be accepted in the standby (powe r save) mode. www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 29/60 6.2 the configuration of serial data at sda termina l is at below msb lsb a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 address r/w address data r/w: establishes the read mode when set to ?1?, and the write mode when set to ?0?. write mode: www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 30/60 6.3 register table when grb is low, all registers reset to default va lues serial commands are executed at next vsync signal ( ) is default register address msb register data (default setting ) lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r0 0 0 0 0 0 0 0 0 y_cbcr (0) ccir601 (0) x x vcac (0) vcom_ac (011) r1 0 0 0 0 0 0 0 1 vcdce (1) 0 vcom_dc (0ah) r3 0 0 0 0 0 0 1 1 brightness (40h) r4 0 0 0 0 0 1 0 0 narrow (0) yuv (0) sel (00) ntsc/pal (10) vdir (1) hdir (1) r5 0 0 0 0 0 1 0 1 drv_freq (0) grb (1) pfm_duty (011) shdb2 (1) shdb1 (1) stb (0) r6 0 0 0 0 0 1 1 0 hblk_en (0) led_current (00) vblk (15h) r7 0 0 0 0 0 1 1 1 hblk(46h) r8 0 0 0 0 1 0 0 0 bl_drv (00) x x x 0 0 0 r12 0 0 0 0 1 1 0 0 pair (00) x cbcr (0) x vdpol (1) hdpol (1) dclkpol (0) r13 0 0 0 0 1 1 0 1 contrast_rgb (40h) r14 0 0 0 0 1 1 0 1 x sub-contrast_r (40h) r15 0 0 0 0 1 1 1 1 x sub-brightness_r (40h) r16 0 0 0 1 0 0 0 0 x sub-contrast_b (40h) r17 0 0 0 1 0 0 0 1 x sub-brightness_b (40h) r21 0 0 0 1 0 1 0 1 led_on_cycle (0111) led_on_ratio (1111) r22 0 0 0 1 0 1 1 0 x x x x x gamma set (1) x x r23 0 0 0 1 0 1 1 1 x x gma_v8(01) x x gma_v4(01) r24 0 0 0 1 1 0 0 0 x x gma_v25(10) x x gma_v16(10) r25 0 0 0 1 1 0 0 1 x x gma_v48(10) x x gma_v36(10) r26 0 0 0 1 1 0 1 0 x x gma_v60(10) x x gma_v55(10) note: 1. ?x? => please set to ?0?. www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 31/60 6.4 register description r0: register address msb register data lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r0 0 0 0 0 0 0 0 0 y_cbcr(0) ccir601 (0) x x vcac(0) vcom_ac(011) vcom_ac: common voltage ac level selection (deviati on 0.1v) vcom_ac vcac d2 d1 d0 d3 voltage (v) 0 0 0 0 3.6 0 0 0 1 3.7 0 0 1 0 3.8 0 0 1 1 3.9 0 1 0 0 4.0 0 1 0 1 4.1 0 1 1 0 4.2(default) 0 1 1 1 4.3 1 0 0 0 4.4 1 0 0 1 4.5 1 0 1 0 4.6 1 0 1 1 4.7 1 1 x x 4.8 frp output vcom_ac ccir601: ccir601 input timing selection ccir601 function 0(default) disable ccir601 (default) 1 enable ccir601. (please refer to the table of r4( sel) for detail description) y_cbcr: y & cbcr exchange position (only valid for 8-bit input yuv640 / yuv720) cbcr(r12[4])=?0? cbcr(r12[4])=?1? y_cbcr=?0? (default) cb0 y0 cr0 y1 cb2 y2 cr2 y3 cr0 y0 cb0 y1 cr2 y2 cb2 y3 y_cbcr=?1? y0 cb0 y1 cr0 y2 cb2 y3 cr2 y0 cr0 y1 cb0 y2 cr2 y3 cb2 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 32/60 r1: register address msb register data lsb no a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r1 0 0 0 0 0 0 0 1 vcdce (1) x vcom_dc (0ah) vcom_dc: common voltage dc level selection (20mv/st ep) d5~d0 vcom dc level (v) 00h 0.1 : : 0ah(default) 0.3(default) : : 3fh 1.36 vcdce: vcom_dc function enable setting vcdce function 0 vcom _dc function disable. the comdc pin is hi-z. 1 vcom_dc function enable. the comdc voltage follow s vcom_dc setting. (default) r3: register address msb register data lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r3 0 0 0 0 0 0 1 1 brightness (40h) brightness: rgb bright level setting, setting accur acy: 1 step / bit d7 ~ d0 brightness gain 00h dark (-64) 40h(default) center (0) (default) ffh bright (+191) www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 33/60 r4: register address msb register data lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r4 0 0 0 0 0 1 0 0 narrow(0) yuv(0) sel(00) ntsc/pal(10) vdir(1) hdir(1) hdir: horizontal scan direction setting hdir function 0 right to left scan 1 left to right scan (default) vdir: vertical scan direction setting vdir function 0 down to up scan 1 up to down scan (default) ntsc/pal: ntsc or pal input mode selection (for ups 052 input timing) ntsc/pal d3 d2 mode 0 0 pal 0 1 ntsc 1 x auto detection (default) sel: input data timing format selection sel ccir601 yuv d5 d4 input timing format 0 0 0 0 ups051 (default) 0 0 0 1 ups052 320 240 0 0 1 x ups052 360 240 0 1 1 0 ccir656 1 1 0 x yuv 640(*) 1 1 1 0 yuv 720(*) (*)please refer to yuv640/yuv720 horizontal timing spec for detailed description. www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 34/60 yuv: yuv (ccir656, yuv640, yuv720) or rgb input sel ection yuv function 0 rgb input ( default) 1 ccir656 / yuv640 / yuv720 input. when this command is sent to asic,it will be execut ed immediately narrow: normal display and narrow display selection . narrow function 0 normal display (default) 1 narrow display narrow=0 narrow=1 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 35/60 r5: register address msb register data lsb no a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r5 0 0 0 0 0 1 0 1 drv_freq(0) grb(1) pfm_duty(011) shdb2(1) shdb1(1) stb(0) stb: standby (power saving) mode setting stb function 0 standby mode (default) 1 normal operation shdb1: shut down for back light power converter shdb1 function 0 the back light power converter is off 1 the back light power converter is controlled by p ower on/off sequence (default) shdb2: shut down for vgh/vgl charge pump shdb2 function 0 vgh/vgl charge pump is always off 1 vgh/vgl charge pump is controlled by power on/off sequence (default) pfm_duty: pfm duty cycle selection for back light p ower converter pfm_duty function d5 d4 d3 pfm duty cycle 0 0 0 50% 0 0 1 60% 0 1 0 65% 0 1 1 70%(default) 1 0 0 75% 1 0 1 80% 1 1 0 85% 1 1 1 90% grb: register reset setting grb function 0 reset all registers to default value 1 normal operation (default) drv_freq: drv signal frequency setting drv_freq drv frequency 0(default) dclk / 64 1 dclk / 128 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 36/60 r6: register address msb register data lsb no a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r6 0 0 0 0 0 1 1 0 hblk_en(0) led_current(00) vblk(15h) vblk: vertical blanking setting ups051, ups052, yuv640 and yuv720 ntsc mode d4 ~ d0 vblk unit 01h 1 15h 21(default) 1fh 31 h (line) ccir656 ntsc mode d4 ~ d0 vblk unit 01h 1 16h 22(default) 1fh 31 h (line) ups052, ccir656 and yuv640 and yuv720 pal mode(vert ical blanking + 3) d4 ~ d0 vblk unit 00h 3 15h 24(default) 1fh 34 h (line) note: v-blanking must be adjusted based on the inpu t data. led_current: adjust led current dc-dc feedback voltage d6 d5 feedback threshold voltage 0 0 0.6v(20ma) (default) 0 1 0.75v(25ma) 1 0 0.45v(15ma) 1 1 0.3v(10ma) www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 37/60 r6 & r7: register address msb register data lsb no a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r6 0 0 0 0 0 1 1 0 hblk_en(0) led_current(00) vblk(15h) r7 0 0 0 0 0 1 1 1 hblk(46h) hblk_en & hblk: horizontal blanking setting hblk_en hblk(d7~d0) hblk unit remark x 32h 50 x 46h 70(default) x ffh 255 dclk(*) ups051 0 x 241(fixed) dclk(*) 1 02h ~ ffh 2 ~ 255 dclk(*) ups052 0 xxh 240(fixed) dclk(*) 1 02h ~ ffh 2 ~ 255 dclk(*) yuv640, yuv720 *the frequency of dclk is different under different input timing. r8: register address msb register data lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r8 0 0 0 0 1 0 0 0 bl_drv(00) x x x x x x bl_drv: backlight driving capability setting d7 d6 bl_drv capability 0 0 normal capability (default) 0 1 2 times the normal capability 1 0 4 times the normal capability 1 1 8 times the normal capability www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 38/60 r12: register address msb register data lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r12 0 0 0 0 1 1 0 0 pair(00) x cbcr(0) x vdpol(1) hdpol(1) dclkpol(0) dclkpol: dclk polarity selection dclkpol function 0 positive polarity (default) 1 negative polarity hdpol: hsync polarity selection hdpol function 0 positive polarity 1 negative polarity (default) vdpol: vsync polarity selection vdpol function 0 positive polarity 1 negative polarity (default) d1 d2 d3 d4 vsync hsync dclk data hdpol=1, vdpol=1, dclkpol=0 d1 d2 d3 d4 vsync hsync dclk data hdpol=0, vdpol=0, dclkpol=1 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 39/60 cbcr: cb & cr exchange position, (please refer to t he table of r0( y_cbcr) for detail description) pair: vertical start time setting for odd/even fram e ups051 / ups052 ntsc / ups052 pal (*) pair vblk d7 d6 odd/even unit x 0 21/21(default) x 1 21/20 h (line) ccir656/yuv640/yuv720 ntsc/pal (**) pair vblk d7 d6 odd/even unit 0 0 22/22(default) 0 1 22/23 1 0 23/22 1 1 23/23 h (line) (*)the typical value of vblk of ups052 pal(24 h) is different than ups051/ups052 ntsc(21h). (**) the typical value of vblk of ccir656 pal(24 h) is different than ccir656 ntsc(22h). note: v-blanking must be adjusted based on the inpu t data. for example: cb0 y0 cr0 y1 cb2 y2 cr2 y3 cbcr=?0? cbcr=?1? cr0 y0 cb0 y1 cr2 y2 cb2 y3 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 40/60 r13: register address msb register data lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r13 0 0 0 0 1 1 0 1 contrast_rgb(40h) contrast_rgb: rgb contrast level setting, the gain changes (1/64) / bit d7 ~ d0 contrast gain 00h 0 40h 1(default) ffh 3.984 r14~r17: register address msb register data lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r14 0 0 0 0 1 1 0 1 x sub-contrast_r(40h) r16 0 0 0 1 0 0 0 0 x sub-contrast_b(40h) sub-contrast: r/b sub-contrast level setting, the g ain changes (1/256) / bit d6 ~ d0 brightness gain 00h 0.75 40h 1(default) 7fh 1.246 dout_g[7:0] = din[7:0] x contrast[ 0 to 1.0 to 3.98 4] dout_r[7:0] = din[7:0] x contrast[ 0 to 1.0 to 3.98 4] x sub-contrast r [0.75 to 1.0 to 1.246] dout_b[7:0] = din[7:0] x contrast[ 0 to 1.0 to 3.98 4] x sub-contrast b [0.75 to 1.0 to 1.246] note: output values above ?255? clipped www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 41/60 register address msb register data lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r15 0 0 0 0 1 1 1 1 x sub-brightness_r(40h) r17 0 0 0 1 0 0 0 1 x sub-brightness_b(40h) sub-brightness: r/b sub-bright level setting, setti ng accuracy: 1 step / bit d6 ~ d0 brightness gain 00h dark (-64) 40h center (0)(default) 7fh bright (+63) dout_g[7:0] = din_g[7:0] + bright[ -64 to 0 to +191 ] dout_r[7:0] = din_r[7:0] + bright[ -64 to 0 to +191 ] + sub-bright r[-64 to 0 to +63] dout_b[7:0] = din_b[7:0] + bright[ -64 to 0 to +191 ] + sub-bright b[-64 to 0 to +63] note: output values below ?0? and above ?255? clipp ed www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 42/60 r21: register address msb register data lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r21 0 0 0 1 0 1 0 1 led_on_cycle (0111) led_on_ratio (1111) led_on_ratio: set the active ratio of enable signal , and we can use it to adjust brightness of the led s. led_on_ratio d3 d2 d1 d0 value 0 0 0 0 1/16 0 0 0 1 2/16 0 0 1 0 3/16 0 0 1 1 4/16 0 1 0 0 5/16 0 1 0 1 6/16 0 1 1 0 7/16 0 1 1 1 8/16 1 0 0 0 9/16 1 0 0 1 10/16 1 0 1 0 11/16 1 0 1 1 12/16 1 1 0 0 13/16 1 1 0 1 14/16 1 1 1 0 15/16 1 1 1 1 16/16(default) led_on_cycle : set the cycle of enable signal , and we can use it to adjust brightness of the leds. led_on_cycle d7 d6 d5 d4 value 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8(default) 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 16 www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 43/60 enable signal disable enable hsync drv cycle 16 led_on_cycle led_on_cycle (led_on_ratio 16 ) led_on_cycle (16 led_on_ratio 16) (cycle) (enable) (disable) unit : hsync for example: led_on_ratio is ?1001? , and led_on_cycle is ?0111? , then: cycle = 16 8 = 128(hsync) enable = 8 (( 10/16 ) 16) = 80(hsync) disable = 8 (16-( 10/16 ) 16) = 48(hsync) 62.5% on r22: register address msb register data lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r22 0 0 0 1 0 1 1 0 x x x x x gamma set (1) x x gamma set: select auto or manual gamma setting gamma set description 0 manual set gamma by r23 ~ r26. 1 auto set to gamma2.2 (default). www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 44/60 r23 ~ r26: register address msb register data lsb no. a6 r/w a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r23 0 0 0 1 0 1 1 1 x x gma_v8 (01) x x gma_v4 (01) r24 0 0 0 1 1 0 0 0 x x gma_v25 (10) x x gma_v16 (10) r25 0 0 0 1 1 0 0 1 x x gma_v48 (10) x x gma_v36 (10) r26 0 0 0 1 1 0 1 0 x x gma_v60 (10) x x gma_v55 (10) 8 adjustable points gamma curve 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 0 8 16 24 32 40 48 56 gray t www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 45/60 c. optical specification (note 1,note 2, note 3 ) item symbol condition min. typ. max. unit remark response time rise fall tr tf =0 ? - - 15 20 25 30 ms ms note 4 contrast ratio cr at optimized viewing angle 200 300 - note 5,6 viewing angle top bottom left right cr R 10 35 50 45 45 45 60 55 55 - - - - deg. note 7 brightness * y l =0 ? 200 250 - cd/m 2 note 8 x =0 ? (0.26) (0.31) (0.36) white chromaticity y =0 ? (0.28) (0.33) (0.38) note 1. ambient temperature =25 . note 2. to be measured in the dark room. note 3.to be measured on the center area of panel w ith a field angle of 1 ? by topcon luminance meter bm-7, after 10 minutes operation. note 4. definition of response time: the output signals of photo detector are measured wh en the input signals are changed from ?black? to ?white?(falling time) and from ?whit e? to ?black?(rising time), respectively. the response time is defined as the time interval bet ween the 10% and 90% of amplitudes. refer to figure as below. s i g n a l ( r e l a t i v e v a l u e ) "black" tr tf "white" "white" 0% 10% 90% 100% www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 46/60 note 5. definition of contrast ratio: contrast ratio is calculated with the following formu la. photo detector output when lcd is at ?white? state photo detector output when lcd is at ?black? state note 6. white vi=v i50 1.5v black vi=v i50 2.0v ? ? means that the analog input signal swings in phas e with com signal. ? ? means that the analog input signal swings out of phase with com signal. v i50 : the analog input voltage when transmission is 50% the 100% transmission is defined as the transmission of lcd panel when all the input terminals of module are electrically opened. note 7. definition of viewing angle: refer to figure as below. note 8. measured at the center area of the panel wh en all the input terminals of lcd panel are electrically opened with driving current under 20ma. note 9. color filter arrangement contrast ratio (cr)= www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 47/60 d. reliability test items no. test items conditions remark 1 high temperature storage ta= 70 240hrs 2 low temperature storage ta= 0 240hrs 3 high temperature operation ta= 60 240hrs 4 low temperature operation ta= 0 240hrs 5 high temperature and high humidity ta= 60 . 90% rh 240hrs operation 6 heat shock 0 ~60 /50 cycle 2hrs/cycle non-operation 7 electrostatic discharge 200v,200pf(0 ), once for each terminal non-operation frequency range : 10~55hz stoke : 1.5mm sweep : 10~55hz~10hz 2 hours for each direction of x,y,z 8 vibration (6 hours for total) non-operation jis c7021, a-10 condition a 9 mechanical shock 100g . 6ms, x, y, z 3 times for each direction non-operation jis c7021, a-7 condition c 10 vibration (with carton) random vibration: 0.015g 2 /hz from 5~200hz ?6db/octave from 200~500hz iec 68-34 11 drop (with carton) height: 60cm 1 corner, 3 edges, 6 surfaces note: ta: ambient temperature. www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 48/60 e. packing form m o d e l ( a 0 3 0 d w 0 1 v 0 ) p et tray www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 49/60 f. outline dimension fig. 1 outline dimension of tft-lcd module www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 50/60 g. application note 1. application circuit 1.1 with internal led driver circuit note1: use internal led driver must set r5[1](shdb1 )= ?1?. www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 51/60 1.2 with external led driver circuit note2: use external led driver must set r5[1](shdb1 )= ?0?. www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 52/60 2. power on/off sequence the register setting of standby mode disabling / en abling is used to control the build-in power on / o ff sequence. 2.1 power on (standby disabling) after vdd power on reset, vsync/hsync/dclk/data can be input, and serial control interface is also operational. the lcd driver is in default standby m ode after vdd power-on, and setting register r5: st b to ?1? to disable the standby mode is required for nor mal operation. when the standby mode is disabled, a build-in power on sequence is started. the lcd posi tive and negative power supplies vgh/vgl are pumped first, and followed by the led power vled. please r efer to fig.12 for the detail timing of power on se quence. fig.12 power on sequence www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 53/60 2.2 power off (standby enabling) when the register stb is set to ?0? to enable stand by mode, a build-in power off sequence is started. please refer to fig.13 for the detail timing of pow er off sequence. fig.13 power off sequence www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 54/60 3. recommended power on/off serial command settings 3.1 ups051 min: 0ms max: 50ms min:1 field power on power off vdd 5eh input serial setting register r5 set standby dclk / hsync / vsync / data input 5 fields (1 field: ntsc=16.6ms; pal=20ms) dclk / hsync / vsync / data input vdd input register r4 0bh set ups051 mode 5fh release standby r5 1eh r5 global reset r5 5eh global reset recovery xxh other registers setting rx min: 0ms www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 55/60 3.2 ups052 320 mode min: 0ms max: 50ms min:1 field power on power off vdd 5eh input serial setting register r5 set standby dclk / hsync / vsync / data input 5 fields (1 field: ntsc=16.6ms; pal=20ms) dclk / hsync / vsync / data input vdd input register r4 1 bh set ups052 320 mode 5fh release standby r5 1eh r5 global reset r5 5eh global reset recovery xxh other registers setting rx min: 0ms www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 56/60 3.3 ups052 360 mode min: 0ms max: 50ms min:1 field power on power off vdd 5eh input serial setting register r5 set standby dclk / hsync / vsync / data input 5 fields (1 field: ntsc=16.6ms; pal=20ms) dclk / hsync / vsync / data input vdd input register r4 2 bh set ups052 360 mode 5fh release standby r5 1eh r5 global reset r5 5eh global reset recovery xxh other registers setting rx min: 0ms www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 57/60 3.4 ccir656 min: 0ms max: 50ms min:1 field power on power off vdd 5eh input serial setting register r5 set standby dclk / hsync / vsync / data input 5 fields (1 field: ntsc=16.6ms; pal=20ms) dclk / hsync / vsync / data input vdd input register r4 6 bh set ccir656 mode 5fh release standby r5 1eh r5 global reset r5 5eh global reset recovery xxh other registers setting rx min: 0ms www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 58/60 3.5 yuv 720 min: 0ms max: 50ms min:1 field r0 43h power on dclk / hsync / vsync / data input vdd input register r4 6bh set yuv 720 mode 5fh release standby r5 1eh r5 global reset r5 5eh global reset recovery xxh other registers setting rx power off vdd 5eh input serial setting register r5 set standby dclk / hsync / vsync / data input 5 fields (1 field: ntsc=16.6ms; pal=20ms) min: 0ms set ccir601=?1? www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 59/60 3.6 yuv 640 min: 0ms max: 50ms min:1 field r0 43h power on dclk / hsync / vsync / data input vdd input register r4 4 bh set yuv 640 mode 5fh release standby r5 1eh r5 global reset r5 5eh global reset recovery xxh other registers setting rx power off vdd 5eh input serial setting register r5 set standby dclk / hsync / vsync / data input 5 fields (1 field: ntsc=16.6ms; pal=20ms) min: 0ms set ccir601=?1? www..net
all rights strictly reserved. any portion of this p rper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a030dw01 v0 product spec version 0.0 page 60/60 4. power generation circuit the black diagram of built-in power generation circ uit for tft-lcd supply power is shown as below: www..net

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